Vhdl Code For 3x8 Decoder

  • By Sandeep Verma – October 12, In the latter case the decoder may be synthesized by means of a hardware description language such as VHDL or Verilog. The interactive 3 to 8 Decoder digital logic circuit, with Boolean function. The phone has three dialing buttons A, B, C and is connected to eight different speakers, as shown in Table 1.
  • Design of 3: 8 Decoder Using When-Else Statement (VHDL Code). 11:55 naresh.dobal 9 comments Email This BlogThis!

A decoder is a combinational circuit constructed with logic gates. It is the reverse of the encoder. A decoder circuit is used to transform a set of digital input signals into an equivalent decimal code of its output. For ‘n’ inputs a decoder gives 2^n outputs. In this article, we will discuss on 4 to 16 decoder circuit design using 3 to 8 decoder.

An encoder is a combinational circuit that changes a set of signals into a code. For ‘2^n’ inputs an encoder circuit gives ‘n’ outputs.

3x8 Decoder In Vhdl can offer you many choices to save money thanks to 10 active results. You can get the best discount of up to 50% off. The new discount codes are constantly updated on Couponxoo. The latest ones are on Jun 23, 2020 5 new 3x8 Decoder In Vhdl results have been found in the last 90 days, which means that every 18, a new 3x8. Question on VHDL 3 to 8 decoder using two 2 to 4 decoders. I have successfully created the code for this problem using port map dec2to4. I'm having trouble with the test bench at the moment. It only gives me the input but the output is only empty. Here is my code for dec3to8:-library IEEE.


The following figure shows the block diagram of a decoder.

Vhdl Code For 3 To 8 Decoder Using If Else Statement

3 to 8 Decoder

This decoder circuit gives 8 logic outputs for 3 inputs. The circuit is designed with AND and NAND combinations. It takes 3 binary inputs and activates one of the eight outputs.

Circuit Diagram

The decoder circuit works only when the Enable pin is high.

Truth Table

When the Enable (E) pin is low, all the output pins are low.


S0S1S2ED0D1D2D3D4D5D6D7
xxx000000000
000100000001
001100000010
010100000100
011100001000
100100010000
101100100000
110101000000
111110000000

Circuit Design of 4 to 16 Decoder Using 3 to 8 Decoder

A decoder circuit of the higher combination is obtained by adding two or more lower combinational circuits. 4 to 16 decoder circuit is obtained from two 3 to 8 decoder circuits or three 2 to 4 decoder circuits.

When two 3 to 8 Decoder circuits are combined the enable pin acts as the input for both the decoders. When enable pin is high at one 3 to 8 decoder circuits then it is low at another 3 to 8 decoder circuit.

Truth Table

The Enable (E) pin acts as one of the input pins for both 3 to 8 decoder circuits.

EABCY0Y1Y2Y3Y4Y5Y6Y7Y8Y9Y10Y11Y12Y13Y14Y15
00000000000000000001
00010000000000000010
00100000000000000100
00110000000000001000
01000000000000010000
01010000000000100000
01100000000001000000
01110000000010000000
10000000000100000000
10010000001000000000
10100000010000000000
10110000100000000000
11000001000000000000
11010010000000000000
11100100000000000000
11111000000000000000

Circuit Diagram of 4 to 16 Decoder

Applications of Decoders

  • In every wireless communication, data security is the main concern. The decoders are mainly designed to provide security for data communication by designing standard encryption and decryption algorithms.
  • Decoders are used in audio systems to convert analogue audio into digital data.
  • Used as a decompressor to convert compressed data like images and videos into decompressed form.
  • Decoders use electronic circuits which convert computer instructions into CPU control signals.

Therefore, this is all about the 4 to 16 decoder circuit design using a 3 to 8 decoder circuit. Furthermore, any queries regarding this article or electronics projects you can comment us in the comment section below. here is a question for you, what is the use of Enable pin encoder/ decoder?

Related Content
The following is the VHDL code for 3x8 decoder in behavioral style along with the test bench.


library IEEE;
entity deco1 is
y : in STD_LOGIC;
d0 : out STD_LOGIC;
d2 : out STD_LOGIC;
d4 : out STD_LOGIC;
d6 : out STD_LOGIC;
end deco1;

component decand1 is
b : in STD_LOGIC;
d : out STD_LOGIC);
component decnot1 is
c : out STD_LOGIC);
signal s2, s1, s3: STD_LOGIC;
g1: decnot1 port map(x,s1);
g3: decnot1 port map(z,s3);
g5: decand1 port map(s1, s2, z, d1);
g7: decand1 port map(s1, y, z, d3);
g9: decand1 port map(x, s2, z, d5);
g11: decand1 port map(x, y, z, d7);

  • TEST BENCH
LIBRARY ieee;
ENTITY deco2_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT deco1
x : IN std_logic;
z : IN std_logic;
d1 : OUT std_logic;
Vhdl Code For 3x8 Decoder
d3 : OUT std_logic;
d5 : OUT std_logic;
d7 : OUT std_logic
END COMPONENT;
--Inputs
signal y : std_logic := '0';

Structural
--Outputs
signal d1 : std_logic;
signal d3 : std_logic;
signal d5 : std_logic;
signal d7 : std_logic;
BEGIN
uut: deco1 PORT MAP (
Vhdl Code For 3x8 Decoder
y => y,
d0 => d0,
d2 => d2,
d4 => d4,
d6 => d6,
);

Vhdl Code For 3x8 Decoder Download


stim_proc: process
x<='0'; y<='0';z<='0';
x<='0'; y<='0';z<='1';
x<='0'; y<='1';z<='0';
x<='0'; y<='1';z<='1'; wait for 100ns;
x<='1'; y<='0';z<='1';wait for 100ns;
x<='1'; y<='1';z<='1';wait for 100ns;

END;

Test Bench Waveform: